PBGA electrical noise isolation of signal traces

ABSTRACT

A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.

FIELD OF THE INVENTION

[0001] The present invention relates to ball grid array typesemiconductor packages, and more particularly to the design of a tracelayout to isolate electrical noise between two adjacent sets of signalsin a 2-layer PBGA substrate.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits are typically packaged before they are usedwith other components as part of a larger electronic system. Ball gridarray (BGA) packages are constructed with die mounted on a substratewith bond pads on the die connected to conductive lines or traces on thesurface substrate. An array of solder balls mounted on the bottom of thesubstrate are used to attach the package to a PC board or motherboard,as opposed to molded plastic packages that use lead frames on the outeredges of the package substrate to attach the package to the PC board.

[0003] A plastic ball grid array (PBGA) is a wire bond package having a2-layer organic substrate and solder balls. FIG. 1A is a cross sectionalview showing the layer stack-up of a typical 2-layer BGA substrate. Thepackage 10 includes a substrate 12, and a die 14 coupled to signaltraces 16 on the top surface of the substrate via wire bonds 22. Thesubstrate 12 typically comprises Bismaleimidie Trizine (BT) or the like.Signal traces 16 on the top layer of the substrate 12 are connected onthe bottom of the substrate 12 through vias 18.

[0004] Although 2-layer PBGA substrates 12 offer a low cost packagingsolution, 2-layer PBGA substrates 12 suffer from electrical noisebetween adjacent sets of signals and coupling interference.

[0005] In order to minimize the electrical noise and the couplinginterference, the normal option is to use a more costly enhanced plasticball grid array (EPBGA). An EPBGA is a wire bond package that uses4-layer organic substrate for better electrical and thermal performance.

[0006]FIG. 1B is a cross sectional view showing the layer stack-up of atypical 4-layer substrate. Layer 1 of the substrate 52 is a top signallayer 54, layer 2 is a ground plane (Vss) 56, layer 3 is a power plane(Vdd) 58, and layer 4 is a bottom signal layer 60. Signal traces aretypically patterned on both the top and bottom signal layers 54 and 60,which are connected to the solder bumps 62 through vias 64. The thickersubstrate 52 and the two extra planes 56 and 58 between the top andbottom layers 54 and 60 help reduce noise. However, a 4-layer EPBGA cost20-30% more than a 2-layer PBGA of a similar design.

[0007] Accordingly, what is needed a method for fabricating asemiconductor package to reduce electrical noise between adjacentsignals in a 2-layer PBGA without adding additional layers. The presentinvention addresses such a need.

SUMMARY OF THE INVENTION

[0008] The present invention provides a method for fabricating asemiconductor package to reduce electrical noise. The semiconductorpackage uses a 2-layer substrate that includes an array of solder ballson the bottom. The method includes patterning signal traces on a toplayer of the substrate and identifying groups of signal traces toisolate. According to the present invention, a grounded isolation traceis then patterned adjacent to one of the groups of traces to isolate thesignal traces, thereby providing noise shielding. In a preferredembodiment, the grounded isolation trace is provided with multiple vias,rather than only one. In a further aspect of the present invention a rowof solder balls is connected together and to ground to create abottom-layer isolating ground trace to further reduce noise. Thebottom-layer isolating ground trace may be connected to the top-layerisolating ground trace using a via.

[0009] According to the system and method disclosed herein, the presentinvention effectively isolates noise between adjacent signals withoutadding additional layers and at low cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1A is a cross sectional view showing a layer stack-up of aconventional 2-layer PBGA substrate.

[0011]FIG. 1B is a cross sectional view showing a layer stack-up of atypical 4-layer substrate.

[0012]FIG. 2 is a flow chart illustrating the method for fabricating asemiconductor package in accordance with a preferred embodiment of thepresent invention.

[0013]FIG. 3 is a diagram of the top view of a customized 2-layer PBGAsubstrate showing a portion of the top signal layer in accordance withthe present invention.

[0014]FIG. 4 is a diagram of the bottom view of the customized 2-layerPBGA substrate showing a portion of the bottom signal layer.

DETAILED DESCRIPTION

[0015] The present invention relates to reducing electrical noise in a2-layer PBGA substrate. The following description is presented to enableone of ordinary skill in the art to make and use the invention and isprovided in the context of a patent application and its requirements.Various modifications to the preferred embodiments and the genericprinciples and features described herein will be readily apparent tothose skilled in the art. Thus, the present invention is not intended tobe limited to the embodiments shown but is to be accorded the widestscope consistent with the principles and features described herein.

[0016] The present invention provides an improved semiconductor packagethat reduces electrical noise in 2-layer PBGA packages. FIG. 2 is a flowchart illustrating the method for fabricating a semiconductor package inaccordance with a preferred embodiment of the present invention. Theprocess begins by patterning a plurality of traces 16 on one or bothsides of a 2-layer PBGA organic substrate 12, which includes solderballs 20 on the bottom layer in step 100. One or more groups of signals16 that need to be isolated due to noise are identified in step 102.

[0017] In accordance with the present invention an isolating groundtrace is patterned on the substrate adjacent and substantially parallelto at least one of the groups of signals 16 to isolate the two groups ofsignals 16 in step 104.

[0018]FIG. 3 is a diagram of the top view of a customized 2-layer PBGAsubstrate showing a portion of the top signal layer, where likereference numerals from FIG. 1A denotes like components. According tothe present invention, at least one isolating ground trace 200 islocated between two groups of signal traces on the substrate 12. In apreferred embodiment, the isolating ground trace 200 is thicker than thesignal traces 16 Referring to both FIGS. 2 and 3, the isolating groundtrace 200 is connected to ground through multiple vias 202 in step 106.In a preferred embodiment, grounding of the isolating trace 200 isachieved by placing a via 202 on both ends of the isolation trace 200.For lengthy grounded isolation traces 200, multiple vias 202 may beplaced along the length of the grounded isolation trace 200 to addfurther shielding. According to the present invention, the groundedisolating trace 200 in effect acts as a local shield between thesignals, thereby protecting the signals from cross talk and achievingnoise reduction without adding additional planes to the substrate.

[0019] Referring again to FIG. 2, in a further aspect of the presentinvention, additional noise shielding is provided by identifying a rowof solder balls 20 to be grounded and connecting the balls 20 togetherand to ground in step 108.

[0020]FIG. 4 is a diagram of the bottom view of the customized 2-layerPBGA substrate showing a portion of the bottom signal layer, where likereference numerals from FIG. 1A denotes like components. The bottom ofthe substrate 12 includes an array of solder balls 20. An isolatingground trace 204 is formed on the bottom layer by connecting a row ofthe solder balls 20. Since the rows of solder balls 20 are parallel toeach other, the bottom-layer isolating ground trace 204 will also beparallel to the other rows of solder balls 20.

[0021] Referring to both FIGS. 2 and 4, in one embodiment, the isolatingground trace 204 on the bottom layer may also be connected to theisolating ground trace 200 on the top layer using multiple via 206 instep 110. By placing isolating traces on the top and bottom layers, thepresent invention isolates signals on both sides of the 2-layersubstrate 12 with minimal interference.

[0022] Accordingly, the present invention enhances electricalperformance of a 2-layer PBGA, while maintaining cost because additionallayers in the substrate are unnecessary to control noise. Furthermore,since the wire bond profile is the same as the adjacent signals, themethod will provide reduced coupling along the wire bond traverse.

[0023] A PBGA semiconductor package having electrical noise Isolation ofsignal traces has been disclosed. The present invention has beendescribed in accordance with the embodiments shown, and one of ordinaryskill in the art will readily recognize that there could be variationsto the embodiments, and any variations would be within the spirit andscope of the present invention. For example, although the method forisolating noise present invention has been described in terms ofwire-bond packaging, the present invention can be used for other typesof packaging where the number of substrate layers need to be kept to aminimum, such as flip-chip, tab, and so on. Accordingly, manymodifications may be made by one of ordinary skill in the art withoutdeparting from the spirit and scope of the appended claims.

What is claimed is: 1 A method for fabricating a semiconductor package,the method including the steps of: (a) providing a 2-layer substrate,the 2-layer substrate including a top layer and a bottom layer whereinthe bottom layer includes an array of solder balls; (b) patterningsignal traces on the top layer; (c) identifying groups of signal tracesto isolate; and (d) patterning a grounded isolation trace adjacent toone of the groups of traces to isolate the signal traces and therebyprovide noise shielding. 2 The method of claim 1 further including thestep of: (e) identifying a row of solder balls to be grounded, and (f)connecting the row of solder balls together and to ground to create abottom-layer isolating ground trace. 3 The method of claim 2 furtherincluding the step of: (g) connecting the bottom-layer isolating groundtrace to the isolating ground trace on the top layer using a via. 4 Themethod of claim 1 wherein step (d) further includes the step of: (i)patterning the grounded isolating trace substantially parallel to thesignal traces. 5 The method of claim 2 wherein step (e) further includesthe step of connecting the isolating ground trace to ground using twovias, wherein one via is located at each end of the isolating groundtrace. 6 The method of claim 3 wherein step (g) further includes thestep of providing multiple vias along the isolating ground trace tofurther reduce noise. 7 A method for fabricating a semiconductorpackage, the method including the steps of: (a) patterning a pluralityof traces on a top layer of a 2-layer PBGA substrate, the substrateincluding an array of solder balls on a bottom layer; (b) identifyingone or more groups of signals that need to be isolated due to noise; (c)patterning an isolating ground trace on the substrate adjacent andsubstantially parallel to at least one of the groups of signals toisolate the two groups of signals; (d) connecting the isolating groundtrace to ground through multiple vias; (e) identifying a row of solderballs to be grounded and connecting the row of solder balls together andto ground to create a bottom-layer isolating ground trace; and (f)connecting the bottom-layer isolating ground trace to the isolatingground trace on the top layer using a via. 8 The method of claim 7further including the step of patterning the isolating ground trace on atop layer of the substrate. 9 The method of claim 8 further includingthe step of providing vias on both ends of the isolating ground trace.10 The method of claim 9 wherein step (d) further includes the step ofproviding a via at each end of the isolating ground trace. 11 The methodof claim 10 wherein step (e) further includes the step of patterning thebottom-layer isolating ground trace on the substrate substantiallyparallel to adjacent rows of solder balls. 12 A package substrate havingnoise control, comprising: at most two layers; a plurality of signaltraces on a first layer; and at least one isolating ground trace on thefirst layer between two signal traces to provide noise shielding. 13 Thepackage of claim 12 wherein the isolating ground trace is connected to aground. 14 The package of claim 13 wherein the substrate includes anarray of solder balls on a second layer such that at least one the rowof solder balls is connected together and to ground to create asecond-layer isolating ground trace. 15 The package of claim 14 whereinthe second-layer isolating ground trace is connected to the isolatingground trace on the first layer using a via. 16 The package of claim 15wherein the isolating ground trace includes multiple vias, with one vialocated on each end of the isolating ground trace. 17 The package ofclaim 16 wherein the isolating ground trace is patterned adjacent andsubstantially parallel to the signal traces on the first layer.